Field effect transistors (“FETs”), such as metal oxide semiconductor field effect transistors (“MOSFETs”), junction field effect transistors (“JFETs”), and double diffused metal-oxide semiconductor (DMOS) transistors etc. are widely used in various electronic products. In certain application circumstances, for example, in power management applications, when the FETs are used as switching elements in power supplies, it is generally desired that the FETs have relatively low on resistance, relatively high breakdown voltage, good current handling capability and good ruggedness.
A field effect transistor (“FET”) may generally be fabricated on a semiconductor substrate and include a core active area and a termination area. The core active area usually comprises at least one FET cell having a gate, a drain region, and a source region. The gate regulates the conduction and blocking of a channel region in the substrate to control an electrical current flow between the drain region and the source region. The termination area should comprise at least one termination cell which serves to isolate the core active area from the termination area, to block undesired electrical leakage path from the termination area to the core active area, and to improve the breakdown voltage (i.e. the maximum drain to source voltage that the FET can assume without breakdown in its OFF state) of the FET. Increasing the number of FET cells formed in the core active area is beneficial to reducing the on resistance and improving the current handling ability of the FET. In the meanwhile, improving the isolation performance and voltage withstand properties of the termination cell(s) formed in the termination area is beneficial to increasing the breakdown voltage and ruggedness of the FET. A FET may be configured to have a planar gate or a trench gate.
Take a trench gate FET 10 for example, as illustrated in the cross sectional view of FIG. 1, the FET 10 is fabricated on an N type semiconductor substrate 101 having an active area 102 and a termination area 103. In the active area 102, FET cells having trenched gates 104, N+ type source regions 105 and P type body regions 106 are formed in the N type semiconductor substrate 101 that functions as a drain region of the FET 10. The trenched gates 104 are electrically connected to each other. The electrical connection of the trenched gates 104 is illustrated by a dotted line in FIG. 1. Each of the trenched gates 104 is isolated from the source regions 105, the body regions 106 and the substrate 101 by a gate oxide lining the bottom and sidewalls of the gate trench. In the termination area 103, a trenched gate contact 107 is formed. The trenched gate contact 107 is electrically connected (the electrical connection still illustrated by a dotted line) to the trenched gates 104 and has a wider trench width than the trenched gates 104 to facilitate connection to a gate metal 108. In the termination area 103, a plurality of trenched isolation cells 109 are further formed to protect the FET cells in the active area 102. Each of the trenched isolation cells 109 has a same or similar structure as each of the trenched gates 104. A thin oxide layer lining the bottom and sidewalls of each trench of the isolation cells 109 isolates the isolation cell 109 from the body regions 106 and the substrate 101. However, the trenched isolation cells 109, especially the innermost one (the one closest to the active cell area 102) may be vulnerable to high drain to source voltage, and may lead to break-down voltage walk-out (i.e. deviation of break-down voltage from designed value) of the FET 10, which is undesirable. FIG. 2 illustrates a simulated equal potential line distribution diagram of a portion of the trenched isolation cells 109 (e.g. a portion corresponding to the BB′ area in FIG. 1) in the FET 10 shown in FIG. 1 when the FET 10 is OFF and a high drain to source voltage (e.g. 30V) is applied between the drain region 101 and the source region 105. It can be seen from FIG. 2 that the equal potential lines near the left side (e.g. the portion looped by the dotted ellipse) of the innermost trenched isolation cell 109 are relatively intensive/close-spaced in comparison with those of other areas, which indicates that the electric field intensity near the left side of the innermost trenched isolation cell 109 is very high. Such a high electric field intensity causes the innermost trenched isolation cell 109 suffer from high voltage pressure, and may lead to walk-out or decrease in break-down voltage of FET 10 or even result in punch-through of the thin oxide layer lining the sidewalls of the trenched termination cell 109, and inducing damage to the FET 10. In addition, in practical application, since the innermost trenched termination cell 109 may suffer from high voltage pressure over and over again during on and off switching of the FET 10, the ruggedness and lifetime of the FET 10 may decrease.